1. Field of the Invention
The present invention relates to methods of manufacturing liquid crystal display (LCD) devices, and more particularly to a method of manufacturing LCD devices having an array substrate uniformly spaced apart from a color filter substrate to define a uniform cell gap.
2. Description of the Related Art
As the development of diverse types of information devices proliferate and become available to consumers, demands on the types of displays used by information devices have increased. Cathode Ray Tubes (CRTs) have been widely used within various information devices due to their functionality and low cost. However, CRTs are not easily made portable nor miniaturized. Due to their beneficial characteristics such as excellent picture quality (e.g., high resolution and luminance), light weight, thin profile, large display area, and low power consumption, LCD devices are commonly used in applications previously dominated by Cathode Ray Tubes (CRTs).
Generally, LCD devices include an array substrate attached to, and spaced apart a predetermined distance from, a color filter substrate to create a cell gap into which liquid crystal material is injected. The array substrate includes a plurality of thin film transistors while the color filter substrate includes a plurality of red (R), green (G), and blue (B) color filters.
Having described the general structure of LCD devices, a method by which LCD devices are generally manufactured will now be described in greater detail.
In fabricating array substrates, a metal layer is deposited onto a transparent glass substrate. Subsequently, in a first masking process, the deposited metal layer is etched to form a gate bus line and a gate electrode. Next, a gate insulating layer, an amorphous silicon layer, and a doped amorphous silicon layer are deposited on the transparent glass substrate supporting the gate bus line and gate electrode. In a second masking process, the deposited gate insulating, amorphous silicon, and doped amorphous silicon layer are patterned to form a channel layer. Next, a source/drain metal layer is deposited on the substrate supporting the channel layer. In a third masking process, the source/drain metal layer is etched to form source/drain electrodes and a data bus line. Next, a protection layer is deposited over the substrate supporting the source/drain electrodes and data bus line. In a fourth masking process, the deposited protection layer is patterned to protect underlying devices and form contact holes. Next, an ITO transparent metal layer is deposited over the substrate supporting the protection layer. In a fifth masking process, the ITO transparent metal layer is etched to form a pixel electrode.
By applying manufacturing techniques methods such as the techniques described above, array substrates can be manufactured using five to eight masking processes. However, as the number of masking processes used to manufacture array substrates increase, the cost associated in manufacturing LCD devices increases. Accordingly, much research has been concentrated on reducing the number of masking processes used in manufacturing array substrates. Currently, for example, array substrates may be manufactured in as few as four masking processes, wherein the channel layer and the source/drain electrodes are patterned in the same masking process.
After the being manufactured, the array substrate is attached to a color filter substrate via a UV-curable sealant material patterned on either the array or color filter substrate. The patterned sealant material generally includes a seal line formed within an interior region of the array substrate and defining a liquid crystal injection hole, enabling liquid crystal material to be injected into the cell gap between the attached array and color filter substrates.
Generally, seal lines are formed on substrates using screen printing methods, dispense printing methods, and the like. According to the screen printing methods, seal lines are formed by applying a roller coated with sealant material against a screen (e.g., a mask) arranged over the substrate. According to the dispense printing methods, seal lines are formed by disposing sealant material within a tube and squeezing the tube above the substrate.
To prevent injected liquid crystal material from seeping out of the cell gap, and to ensure maximized attachment to the color filter substrate, auxiliary seal lines are generally formed in peripheral regions of the array substrate. To maintain a substantially uniform cell gap, spacers can be distributed on the color filter substrate when seal lines are formed on the array substrate. After attaching the array and color filter substrates, the seal lines are cured (e.g., hardened) in the presence of ultraviolet light.
FIG. 1 illustrates a sectional view of a related art LCD device.
Referring to FIG. 1, the array substrate includes a lower substrate 1a, formed of a transparent insulating material that supports a plurality of gate bus lines, a plurality of data bus lines crossing the plurality of gate bus lines, a plurality of pixel regions defined by the crossings of the gate and data bus lines, a plurality of pixel electrodes 2 formed of transparent metal and arranged in a matrix pattern within corresponding ones of the pixel regions, and a first protection layer 3 formed on the lower substrate 1a. The color filter substrate includes a transparent upper substrate 1b, formed of a transparent insulating material that supports a black matrix layer, red (R), green (G), and (B) color filters 9 arranged on the black matrix layer, a second protection layer 7 formed on the R, G, and B color filters 9, and a common electrode 6 formed on the second protection layer 7. A seal line 10 is formed between the array and color filter substrates to seal a liquid crystal layer 5 interposed between the array and color filter substrates and within the cell gap. Ultraviolet light is used to cure the seal line 10, wherein the two substrates are attached to each other by the cured seal line 10.
FIG. 2 schematically illustrates related art seal lines formed on a related art array substrate.
Referring to FIG. 2, each array substrate 21 is manufactured according to the aforementioned four-mask process and includes a plurality of pixel regions (not shown) provided on a transparent insulating substrate 20 and pad regions (not shown) where signals are applied to gate and data bus lines defining the pixel regions. Depending on the size of the transparent insulating substrate 20, four to six array substrates 21 of predetermined sizes can be formed on the same transparent insulating substrate 20.
As mentioned above, patterned sealant material facilitates the attachment of an array substrate 21 to a corresponding color filter substrate. Accordingly, the sealant pattern on each array substrate 21 includes a main seal line 23 formed at an interior region of the array substrate 21 and defining a liquid crystal injection hole, and three auxiliary seal lines 25a, 25b, and 25c and auxiliary seal lines 25′ formed at opposing peripheral regions of the array substrate 21 including a region near the liquid crystal injection hole. The auxiliary seal lines 25a, 25b, 25c, and 25′ prevent the propagation of cracks within the transparent insulating substrate 21, that may be generated during a subsequent scribing process, from peripheral regions of the transparent insulating substrate 20 into the interior region of the array substrate 21.
Related art array substrates such as those shown in FIGS. 1 and 2 generally include a metal protection pattern 27 formed within the peripheral regions of the array substrate 21 where the auxiliary seal lines 25a, 25b, and 25c are formed. The metal protection pattern 27 prevents corner regions of the array substrate 21 from becoming damaged during the masking process used to form the source/drain electrode and the channel layer. Accordingly, the metal protection pattern 27 is patterned in the same masking process as when the source/drain electrode is formed.
As shown in FIG. 2, the first auxiliary seal line 25a completely overlaps the metal protection pattern 27, the second auxiliary seal line 25b partially overlaps the metal protection pattern 27, and the third auxiliary seal line 25c does not overlap the metal protection pattern 27.
FIG. 3 illustrates a cross sectional view of the cell gap maintained by the related art array substrate and seal lines shown in FIG. 2.
Referring to FIG. 3, the main seal line 23, having a predetermined thickness, is formed over a first layered structure including a 2500 Å thick gate electrode metal layer 31 formed on the transparent insulating substrate 20, a 4000 Å thick gate insulating layer 32 formed on the gate electrode metal layer 31, and a 2000 Å thick protection layer 33 formed on the gate insulating layer 32, wherein the main seal line 23 is formed on the protection layer 33. The first layered structure has a step height of 8500 Å above the transparent insulating substrate 20.
The first auxiliary seal line 25a, having the predetermined thickness, is formed over a second layered structure including the 4000 Å thick gate insulating layer 32 formed on the transparent insulating substrate 20, a 2000 Å thick active layer 35 formed on the gate insulating layer 32, the 2000 Å thick metal protection pattern 27 formed on the active layer 35, and the 2000 Å thick protection layer 33 formed on the metal protection pattern 27, wherein the first auxiliary seal line 25a is formed on the protection layer 33. The second layered structure has a step height of 10000 Å above the transparent insulating substrate 20.
The second and third auxiliary seal lines 25b and 25c, respectively, each having the predetermined thickness, are formed over third layered structures including the 4000 Å thick gate insulating layer 32 formed on the transparent insulating substrate 20 and the 2000 Å thick protection layer 33 formed on the gate insulating layer 32, wherein the second and third auxiliary seal lines 25b and 25c, respectively, are formed on the protection layer 33. The third layered structures both have step heights of 6000 Å above the transparent insulating substrate 20.
After the main seal line 23 and the first through third auxiliary seal lines 25a, 25b, and 25c are formed on the array substrate 21, the color filter substrate 30 is attached to the array substrate 21 to form a liquid crystal cell. As mentioned above, when array substrates of LCD devices are manufactured according to the four-mask manufacturing process, the metal protection pattern 27 is formed within the peripheral regions of the liquid crystal injection hole where the auxiliary seal lines 25a, 25b, and 25c are formed. Due to the presence of the metal protection pattern 27, the step height of the second layered structure is greater than the step height of the first or third layered structures. Accordingly, the color filter substrate 30 attaches to the array substrate 21 via the first auxiliary seal line 25a only.
Since the height of the first auxiliary seal line 25a formed in a peripheral region of the array substrate 21, near the liquid crystal injection hole, is 1500 Å greater than the height of the main seal line 23, formed at the interior region of the array substrate 21 and defining the liquid crystal injection hole, a uniform cell gap between the array and color filter substrates cannot be adequately maintained. Further, since the first auxiliary seal line 25a is elevationally higher than the main seal line 23, liquid crystal material may seep out of the liquid crystal cell substrate while being injected. Lastly, spots may deleteriously be generated within the main seal line 23.